Synopsys Generic Technology Mapper, Version mapact, Build 976R, Built May 23 2013 12:10:32 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version H-2013.03M-1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 57MB) @N:MF249 : | Running in 32-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 56MB peak: 58MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 58MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 60MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) @N: : twomult_8_tap_fir.vhd(239) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst Coef_rdaddr[4:0] @N: : twomult_8_tap_fir.vhd(270) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst inp_rdaddr[4:0] @N: : twomult_8_tap_fir.vhd(182) | Found counter in view:work.TwoMult_8_tap_FIR(twomult_8_tap_fir_arch) inst inp_wraddr[5:0] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[0], because it is equivalent to instance Coef_rdaddr1[0] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[1], because it is equivalent to instance Coef_rdaddr1[1] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[2], because it is equivalent to instance Coef_rdaddr1[2] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[3], because it is equivalent to instance Coef_rdaddr1[3] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[4], because it is equivalent to instance Coef_rdaddr1[4] @W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[0], because it is equivalent to instance inp_rdaddr1[0] @W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[1], because it is equivalent to instance inp_rdaddr1[1] @W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[2], because it is equivalent to instance inp_rdaddr1[2] @W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[3], because it is equivalent to instance inp_rdaddr1[3] @W:BN132 : twomult_8_tap_fir.vhd(284) | Removing instance inp_rdaddr2[4], because it is equivalent to instance inp_rdaddr1[4] @W:BN132 : twomult_8_tap_fir.vhd(256) | Removing instance Coef_rdaddr2[5], because it is equivalent to instance inp_rdaddr2[5] Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.47ns 22 / 113 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.47ns 21 / 113 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.47ns 21 / 113 ------------------------------------------------------------ @N:FP130 : | Promoting Net clk_c on CLKINT I_12 @N:FP130 : | Promoting Net reset_n_c on CLKINT I_13 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 79MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 119 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 119 inp_wraddr[0] ======================================================================================= ===== Gated/Generated Clocks ===== ************** None ************** ---------------------------------- ================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base D:\Mathblock\SF2 DSP Application Notes\DSP Reference Guide\Ref. Guide Design Examples\VHDL\Filters\Semi- Parallel FIR filters\Two Multiplier 8-Tap FIR\TwoMult_8Tap_FIR\synthesis\TwoMult_8_tap_FIR.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 79MB) Writing EDIF Netlist and constraint files H-2013.03M-1 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 76MB peak: 79MB) @W:MT246 : inp_ram_inp_ram_0_uram.vhd(89) | Blackbox RAM64x18 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock TwoMult_8_tap_FIR|clk with period 2.53ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Nov 11 16:03:54 2013 # Top view: TwoMult_8_tap_FIR Requested Frequency: 395.2 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -0.447 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------- TwoMult_8_tap_FIR|clk 395.2 MHz 335.9 MHz 2.531 2.977 -0.447 inferred Autoconstr_clkgroup_0 System 1211.1 MHz 1029.4 MHz 0.826 0.971 -0.146 system system_clkgroup ================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------- System System | 0.826 -0.146 | No paths - | No paths - | No paths - System TwoMult_8_tap_FIR|clk | 2.531 1.337 | No paths - | No paths - | No paths - TwoMult_8_tap_FIR|clk System | 2.531 -0.084 | No paths - | No paths - | No paths - TwoMult_8_tap_FIR|clk TwoMult_8_tap_FIR|clk | 2.531 -0.447 | No paths - | No paths - | No paths - ===================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: TwoMult_8_tap_FIR|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------- Coef_rdaddr[0] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[0] 0.094 -0.447 Coef_rdaddr[1] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[1] 0.094 -0.231 Coef_rdaddr[2] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[2] 0.094 -0.127 clr TwoMult_8_tap_FIR|clk SLE Q clr 0.094 -0.084 Coef_rdaddr[3] TwoMult_8_tap_FIR|clk SLE Q Coef_rdaddr[3] 0.094 -0.039 inp_wraddr[0] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[0] 0.094 -0.031 inp_wraddr[1] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[1] 0.094 -0.014 inp_wraddr[2] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[2] 0.094 -0.002 inp_wraddr[3] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[3] 0.094 -0.002 inp_wraddr[4] TwoMult_8_tap_FIR|clk SLE Q inp_wraddr[4] 0.094 -0.002 =================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------- Coef_rdaddr[0] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447 Coef_rdaddr[1] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447 Coef_rdaddr[2] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447 Coef_rdaddr[3] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447 Coef_rdaddr[4] TwoMult_8_tap_FIR|clk SLE EN Coef_rdaddre 2.237 -0.447 U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[0] clr_i_0 2.531 -0.084 U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[0] clr_i_0 2.531 -0.084 U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[1] clr_i_0 2.531 -0.084 U2.multacc_0.U0 TwoMult_8_tap_FIR|clk MACC P_SRST_N[1] clr_i_0 2.531 -0.084 inp_wraddr[5] TwoMult_8_tap_FIR|clk SLE D inp_wraddr_s[5] 2.309 -0.031 ============================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.531 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.237 - Propagation time: 2.684 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.446 Number of logic level(s): 2 Starting point: Coef_rdaddr[0] / Q Ending point: Coef_rdaddr[0] / EN The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ Coef_rdaddr[0] SLE Q Out 0.094 0.094 - Coef_rdaddr[0] Net - - 0.858 - 6 Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 - Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 - N_102 Net - - 0.548 - 2 Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 - Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 - Coef_rdaddre Net - - 0.603 - 5 Coef_rdaddr[0] SLE EN In - 2.684 - ========================================================================================== Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 2.531 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.237 - Propagation time: 2.684 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.446 Number of logic level(s): 2 Starting point: Coef_rdaddr[0] / Q Ending point: Coef_rdaddr[1] / EN The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ Coef_rdaddr[0] SLE Q Out 0.094 0.094 - Coef_rdaddr[0] Net - - 0.858 - 6 Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 - Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 - N_102 Net - - 0.548 - 2 Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 - Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 - Coef_rdaddre Net - - 0.603 - 5 Coef_rdaddr[1] SLE EN In - 2.684 - ========================================================================================== Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 2.531 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.237 - Propagation time: 2.684 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.446 Number of logic level(s): 2 Starting point: Coef_rdaddr[0] / Q Ending point: Coef_rdaddr[4] / EN The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ Coef_rdaddr[0] SLE Q Out 0.094 0.094 - Coef_rdaddr[0] Net - - 0.858 - 6 Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 - Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 - N_102 Net - - 0.548 - 2 Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 - Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 - Coef_rdaddre Net - - 0.603 - 5 Coef_rdaddr[4] SLE EN In - 2.684 - ========================================================================================== Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 2.531 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.237 - Propagation time: 2.684 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.446 Number of logic level(s): 2 Starting point: Coef_rdaddr[0] / Q Ending point: Coef_rdaddr[3] / EN The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ Coef_rdaddr[0] SLE Q Out 0.094 0.094 - Coef_rdaddr[0] Net - - 0.858 - 6 Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 - Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 - N_102 Net - - 0.548 - 2 Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 - Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 - Coef_rdaddre Net - - 0.603 - 5 Coef_rdaddr[3] SLE EN In - 2.684 - ========================================================================================== Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 2.531 - Setup time: 0.293 + Clock delay at ending point: 0.000 (ideal) = Required time: 2.237 - Propagation time: 2.684 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -0.446 Number of logic level(s): 2 Starting point: Coef_rdaddr[0] / Q Ending point: Coef_rdaddr[2] / EN The start point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK The end point is clocked by TwoMult_8_tap_FIR|clk [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ Coef_rdaddr[0] SLE Q Out 0.094 0.094 - Coef_rdaddr[0] Net - - 0.858 - 6 Coef_rdaddr_n3_i_o3 CFG4 D In - 0.952 - Coef_rdaddr_n3_i_o3 CFG4 Y Out 0.384 1.336 - N_102 Net - - 0.548 - 2 Coef_rdaddr_n3_i_o3_RNIG78T CFG3 C In - 1.884 - Coef_rdaddr_n3_i_o3_RNIG78T CFG3 Y Out 0.196 2.080 - Coef_rdaddre Net - - 0.603 - 5 Coef_rdaddr[2] SLE EN In - 2.684 - ========================================================================================== Total path delay (propagation time + setup) of 2.977 is 0.968(32.5%) logic and 2.009(67.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[0] Coef_rddata1[0] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[1] Coef_rddata1[1] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[2] Coef_rddata1[2] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[3] Coef_rddata1[3] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[4] Coef_rddata1[4] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[5] Coef_rddata1[5] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[6] Coef_rddata1[6] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[7] Coef_rddata1[7] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[8] Coef_rddata1[8] 0.000 -0.146 U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 System RAM64x18 A_DOUT[9] Coef_rddata1[9] 0.000 -0.146 =============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------- U0.multadder_0.U0 System MACC A[0] inp_rddata1[0] 0.826 -0.146 U0.multadder_0.U0 System MACC A[0] inp_rddata1[0] 0.826 -0.146 U1.multadder_0.U0 System MACC A[0] inp_rddata2[0] 0.826 -0.146 U1.multadder_0.U0 System MACC A[0] inp_rddata2[0] 0.826 -0.146 U0.multadder_0.U0 System MACC A[1] inp_rddata1[1] 0.826 -0.146 U0.multadder_0.U0 System MACC A[1] inp_rddata1[1] 0.826 -0.146 U1.multadder_0.U0 System MACC A[1] inp_rddata2[1] 0.826 -0.146 U1.multadder_0.U0 System MACC A[1] inp_rddata2[1] 0.826 -0.146 U0.multadder_0.U0 System MACC A[2] inp_rddata1[2] 0.826 -0.146 U1.multadder_0.U0 System MACC A[2] inp_rddata2[2] 0.826 -0.146 ============================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.826 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.826 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.146 Number of logic level(s): 0 Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[0] Ending point: U0.multadder_0.U0 / B[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[0] Out 0.000 0.000 - Coef_rddata1[0] Net - - 0.971 - 1 U0.multadder_0.U0 MACC B[0] In - 0.971 - =================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.826 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.826 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.146 Number of logic level(s): 0 Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[1] Ending point: U0.multadder_0.U0 / B[1] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[1] Out 0.000 0.000 - Coef_rddata1[1] Net - - 0.971 - 1 U0.multadder_0.U0 MACC B[1] In - 0.971 - =================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 0.826 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.826 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.146 Number of logic level(s): 0 Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[2] Ending point: U0.multadder_0.U0 / B[2] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[2] Out 0.000 0.000 - Coef_rddata1[2] Net - - 0.971 - 1 U0.multadder_0.U0 MACC B[2] In - 0.971 - =================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 0.826 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.826 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.146 Number of logic level(s): 0 Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[3] Ending point: U0.multadder_0.U0 / B[3] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[3] Out 0.000 0.000 - Coef_rddata1[3] Net - - 0.971 - 1 U0.multadder_0.U0 MACC B[3] In - 0.971 - =================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 0.826 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 0.826 - Propagation time: 0.971 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.146 Number of logic level(s): 0 Starting point: U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 / A_DOUT[4] Ending point: U0.multadder_0.U0 / B[4] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- U3.Coef_RAM_0.Coef_RAM_Coef_RAM_0_URAM_R0C0 RAM64x18 A_DOUT[4] Out 0.000 0.000 - Coef_rddata1[4] Net - - 0.971 - 1 U0.multadder_0.U0 MACC B[4] In - 0.971 - =================================================================================================================== Total path delay (propagation time + setup) of 0.971 is 0.000(0.0%) logic and 0.971(100.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for TwoMult_8_tap_FIR Mapping to part: m2s050fbga896-1 Cell usage: CLKINT 2 uses RAM64x18 2 uses CFG1 4 uses CFG2 4 uses CFG3 3 uses CFG4 4 uses Carry primitives used for arithmetic functions: ARI1 6 uses Sequential Cells: SLE 113 uses Registers not packed on I/O Pads: 113 DSP Blocks: 3 MACC: 3 Mults I/O ports: 65 I/O primitives: 65 INBUF 21 uses OUTBUF 44 uses Global Clock Buffers: 2 RAM/ROM usage summary Block Rams (RAM64x18) : 2 Total LUTs: 15 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 32MB peak: 79MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Mon Nov 11 16:03:54 2013 ###########################################################]